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Here a list of the TLM-2.0 resources available right here on the Doulos website: TLM-2.0 Base Protocol Checker This open-source protocol checker will help you create models that are compliant to the TLM-2.0 standard; Complete TLM-2.0 AT Example (advanced level); What's New in TLM-2.0.1?
run with TLM2.0-draft-1 or TLM2.0-draft-2, which are incompatible with the final release. The only other thing you need is a supported C++ compiler. Alternatively, you can use a dedicated SystemC simulator, although you will have to pay real money for one of those. Modeling Concepts
The TLM-2.0 Standard CONTENTS • Review of SystemC and TLM • Review of TLM-2.0 • Frequently Asked Questions
s 4 • Loosely-timed = as fast as possible Register-accurate • Only sufficient timing detail to boot O/S and run multi-core systems • b_transport - each transaction completes in one function call
Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial Nils Bosbach, RWTH Aachen University Lukas Jünger, MachineWare GmbH Rainer Leupers, RWTH Aachen University
©2007 Open SystemC Initiative (OSCI) 1 Transaction Level Modeling using OSCI TLM 2.0 By Marcelo Montoreano, Synopsys, Inc. May 31, 2007 1. Introduction
Title: An Insider's View on the Making of the New TLM-2.0 Standard Author: Bart Vanthournout, TLM Working Group Chairman, OSCI Created Date: 5/30/2008 3:51:00 PM
The TLM 2.0 transaction level modeling standard from the Open SystemC Initiative (OSCI) was released on 9th June 2008. Transaction-level modeling (TLM) is a high-level modern approach to modeling digital systems.
TLM2.0 is used to model bus-like transactions as you have in APB, AHB, AXI or alike. It abstracts those transactions in to e.g. read and write with some attribites (liek protection and alike). This saves some from dealing with bit wiggling and, as you have less events, improves simulation performance.
The release of the TLM2 standard enables many new technologies; co-emulation is a major beneficiary. As you move from an untimed high level architectural model to the more detailed RTL representation of your virtual prototype, performance drop-off is expected. With co-emulation you can regain the performance needed to do system level tasks as ...